Estimating delay deterioration due to device degradation in integrated circuits

ABSTRACT

A system for estimating delay deterioration in an integrated circuit includes a degradation estimator for estimating degradation for each of one or more lifetimes in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the integrated circuit. A netlist generator generates an end-of-life netlist for each of the one or more lifetimes in which the at least one device characteristic of each device has been modified to reflect each of the estimated degradations. A timing analyzer performs a timing analysis on each of the end-of-life netlists to determine static or statistical circuit path delays over the one or more lifetimes.

RELATED APPLICATION DATA

This application is a Divisional application of co-pending U.S. patentapplication Ser. No. 13/611,261 filed on Sep. 12, 2012, which in turn isa Continuation application of co-pending U.S. patent application Ser.No. 13/428,571 filed on Mar. 23, 2012, incorporated herein by referencein its entirety.

BACKGROUND

1. Technical Field

The present invention relates to the reliability of integrated circuits,and more particularly to a method for estimating delay deterioration inintegrated circuits due to device degradation.

2. Description of the Related Art

Very large scale integration (VLSI) circuits are designed andmanufactured using imperfect processes and numerous tests must be run tocheck the functionality of a VLSI circuit. Such circuits degrade withuse over time due to known and predictable effects such as biastemperature instability (BTI) and hot carrier injection (HCI). As aresult, manufactured VLSI circuits are more likely to fail in the field,even though they have successfully passed numerous functional andverification tests prior to shipping.

The degradation of individual devices within a VLSI circuit may manifestitself as a change from nominal values established at the timeproduction in one or more characteristics of a device. As an example,degradation may manifest itself as a change from the nominal value of adevice's threshold-voltage or mobility.

A precise estimate of degradation in a VLSI circuit is nearly impossibledue to such factors as highly complex designs, variations inmanufacturing processes, multiple operating environments andapproximations made during the modeling of these circuits. Anover-estimation of a device's degradation may not take into account thatdevice's ability to recover from the effects HCI and BTI degradation orthat device's higher slope times which may compensate for degradation.As a result, excessive guardbands may be applied and good dies on whichVLSI circuits may be formed are wasted. On the other hand, anunder-estimation of a device's degradation may result in not fullytesting certain critical pathways within a circuit. As a result, theeventual degradation of devices within a packaged integrated circuit mayactually occur at a customer location even though the device passedfunctional and verification tests prior to shipping.

SUMMARY

In accordance with the present principles, a system for estimating delaydeterioration in an integrated circuit includes a degradation estimatorfor estimating static or statistical degradation for each of one or morelifetimes in at least one characteristic of each device defined withinthe integrated circuit using voltages and logic values monitored duringa simulation of the integrated circuit, a netlist generator forgenerating an end-of-life netlist for each of the one or more lifetimesin which the at least one device characteristic of each device has beenmodified to reflect each of the estimated degradations and a timinganalyzer for performing a static or statistical timing analysis on eachof the end-of-life netlists to determine static or statistical circuitpath delays over the one or more lifetimes.

A system for estimating delay deterioration in an integrated circuitincludes a degradation estimator for estimating future degradation foreach of one or more lifetimes in at least one characteristic of eachdevice defined within the integrated circuit using voltages and logicvalues monitored during a simulation of the integrated circuit. Anetlist generator generates an end-of-life netlist for each of the oneor more lifetimes, based on an original netlist file that describes thedevices included in the integrated circuit, in which the at least onedevice characteristic of each device has been modified to reflect eachof the estimated degradations. A timing analyzer performs a first timinganalysis on the original netlist file and one or more second timinganalyses on each of the end-of-life netlists to determine static orstatistical circuit path delays over the one or more lifetimes.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a block/flow diagram of a system/method for determining theimpact of aging on timing performance for one or more lifetimes inintegrated circuits according to the embodiments of the presentprinciples;

FIG. 2 is a block/flow diagram of a system/method for estimating delaydeterioration for one or more lifetimes in integrated circuits due todegradation according to the embodiments of the present principles;

FIG. 3 is a block/flow diagram of a system/method demonstrating anend-of-life statistical timing analysis according to an embodiment ofthe present principles;

FIG. 4 is a block/flow diagram of a system/method for estimating delaydeterioration for one or more lifetimes in integrated circuits due todevice degradation according to the embodiments of the presentprinciples; and

FIG. 5 illustrates a computing system for implementing the methods ofestimating delay deterioration for one or more lifetimes in integratedcircuits due to device degradation according to the embodiments of thepresent principles.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

According to the embodiments of the present principles, a method andsystem are provided for estimating the extent of degradation in a deviceat different lifetimes and translating that estimate into a change incircuit performance and shipping frequency. The methods includeexercising a circuit using either a specific pattern or a random patternrepresentative of a workload to be seen by the circuit, performing asimulation to estimate circuit activity and evaluating the possibledegradation in the various devices within the circuit at differentlifetimes. As a further feature of the embodiments of the presentprinciples, the method provides for utilizing static and statisticaltiming analysis to evaluate circuit path delays resulting fromdegradation.

As will be appreciated by one skilled in the art, aspects of the presentinvention may be embodied as a system, method or computer programproduct. Accordingly, aspects of the present invention may take the formof an entirely hardware embodiment, an entirely software embodiment(including firmware, resident software, micro-code, etc.) or anembodiment combining software and hardware aspects that may allgenerally be referred to herein as a “circuit,” “module” or “system.”Furthermore, aspects of the present invention may take the form of acomputer program product embodied in one or more computer readablemedium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may beutilized. The computer readable medium may be a computer readable signalmedium or a computer readable storage medium. A computer readablestorage medium may be, for example, but not limited to, an electronic,magnetic, optical, electromagnetic, infrared, or semiconductor system,apparatus, or device, or any suitable combination of the foregoing. Morespecific examples (a non-exhaustive list) of the computer readablestorage medium would include the following: an electrical connectionhaving one or more wires, a portable computer diskette, a hard disk, arandom access memory (RAM), a read-only memory (ROM), an erasableprogrammable read-only memory (EPROM or Flash memory), an optical fiber,a portable compact disc read-only memory (CD-ROM), an optical storagedevice, a magnetic storage device, or any suitable combination of theforegoing. In the context of this document, a computer readable storagemedium may be any tangible medium that can contain, or store a programfor use by or in connection with an instruction execution system,apparatus, or device.

A computer readable signal medium may include a propagated data signalwith computer readable program code embodied therein, for example, inbaseband or as part of a carrier wave. Such a propagated signal may takeany of a variety of forms, including, but not limited to,electro-magnetic, optical, or any suitable combination thereof. Acomputer readable signal medium may be any computer readable medium thatis not a computer readable storage medium and that can communicate,propagate, or transport a program for use by or in connection with aninstruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmittedusing any appropriate medium, including but not limited to wireless,wireline, optical fiber cable, RF, etc., or any suitable combination ofthe foregoing. Computer program code for carrying out operations foraspects of the present invention may be written in any combination ofone or more programming languages, including an object orientedprogramming language such as Java, Smalltalk, C++ or the like andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The program codemay execute entirely on the user's computer, partly on the user'scomputer, as a stand-alone software package, partly on the user'scomputer and partly on a remote computer or entirely on the remotecomputer or server. In the latter scenario, the remote computer may beconnected to the user's computer through any type of network, includinga local area network (LAN) or a wide area network (WAN), or theconnection may be made to an external computer (for example, through theInternet using an Internet Service Provider).

Aspects of the present invention are described below with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems) and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer program instructions. These computer program instructions maybe provided to a processor of a general purpose computer, specialpurpose computer, or other programmable data processing apparatus toproduce a machine, such that the instructions, which execute via theprocessor of the computer or other programmable data processingapparatus, create means for implementing the functions/acts specified inthe flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computerreadable medium that can direct a computer, other programmable dataprocessing apparatus, or other devices to function in a particularmanner, such that the instructions stored in the computer readablemedium produce an article of manufacture including instructions whichimplement the function/act specified in the flowchart and/or blockdiagram block or blocks. The computer program instructions may also beloaded onto a computer, other programmable data processing apparatus, orother devices to cause a series of operational steps to be performed onthe computer, other programmable apparatus or other devices to produce acomputer implemented process such that the instructions which execute onthe computer or other programmable apparatus provide processes forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof code, which comprises one or more executable instructions forimplementing the specified logical function(s). It should also be notedthat, in some alternative implementations, the functions noted in theblock may occur out of the order noted in the figures. For example, twoblocks shown in succession may, in fact, be executed substantiallyconcurrently, or the blocks may sometimes be executed in the reverseorder, depending upon the functionality involved. It will also be notedthat each block of the block diagrams and/or flowchart illustration, andcombinations of blocks in the block diagrams and/or flowchartillustration, can be implemented by special purpose hardware-basedsystems that perform the specified functions or acts, or combinations ofspecial purpose hardware and computer instructions

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a block/flow diagram isillustrated of a diagram of a system/method for determining the impactof aging on timing performance for one or more lifetimes in integratedcircuits according to the embodiments of the present principles. Inblock 110, a first timing analysis of a defined circuit is performed.The timing analysis establishes circuit path delays at the design phaseof the defined circuit using nominal values for characteristics of eachdevice within the defined circuit.

In block 120, degradation of a device within the defined circuit ispredicted. Degradation may be represented as a change in one or morecharacteristics of a device from their nominal values resulting from useover time. One such characteristic (e.g.) is the threshold-voltage of adevice. Threshold-voltage is a voltage level at which an event occurswithin a device such as the formation of a channel within a field effecttransistor (FET).

A functional expression for a change in threshold-voltage can beexpressed as

ΔVT=f(V _(dd) ,T,t _(on) ,t _(off) ,s),

where V_(dd) is the operating voltage, T is the operating temperature,t_(or), and t_(off) are the on and off duration times and s is thetransition slew. Degradation models, such as a BTI and HCI models, basedon a change in threshold-voltage may be generated using this functionalexpression. These models may reflect operating conditions and activityprofiles of a device. Furthermore, these models may be used to calculatea change in threshold-voltage at different lifetimes.

In order to predict degradation, the circuit definition is simulatedusing a specific pattern and the voltages and logic values at the nodesof each device are monitored at each tine instant during the timespan ofthe simulation. The specific pattern is generated to reflect a workloadthat is to be seen by the integrated circuit under expected operatingconditions. The information derived from the monitored voltages andlogic values is then used in conjunction with a degradation model topredict degradation over one or more lifetimes of an integrated circuit.Once device degradation has been determined for a specified lifetime, anamended circuit definition including the predicted degradation isgenerated for that specified lifetime. As an example, a change in adevice's threshold-voltage as a result of degradation at a specifiedlifetime is incorporated into a modified netlist for that specifiedlifetime. A separate modified circuit definition is generated for eachspecified lifetime.

In block 130, a second timing analysis is performed on each of themodified circuit definitions. These timing analyses determine changes incircuit path delays resulting from degradation for each of thelifetimes.

A timing analysis in the embodiments of the present principles may bestatic or statistical. A static timing analysis is performed usingdevice characteristics represented as single fixed-point values andprovides a deterministic single fixed-point value for correspondingcircuit path delays. However, a static timing analysis does not takeinto account either variations due to imperfect manufacturing processesor variations in the operating environment to which an integratedcircuit may be exposed. To take these variations into account, theembodiments of the present principles also implement a timing analysisthat is statistical. A statistical timing analysis replaces staticdeterministic circuit path timing for a single device with a probabilitydistribution of timings for the single device. As such, a statisticaltiming analysis is based on device characteristics presented as adistribution of possible values. As an example, a device'sthreshold-voltage may be presented as a distribution of values for thatdevice (e.g. a histogram). A person of ordinary skill in the art willnote that other device characteristics, other than threshold-voltage,may be used to estimate degradation including, but limited to, mobility.

Referring now to FIG. 2, a block/flow diagram illustrates asystem/method for estimating delay deterioration for one or morelifetimes in integrated circuits due to degradation according to theembodiments of the present principles. In block 210, an original netlistdefining an integrated circuit is provided. A netlist file describes thedevices included in a circuit that is to be simulated and provides adefinition for each of these devices. The devices defined within theoriginal netlist may include both analog and digital devices. Thedefinition of these devices includes a listing of possible connectionsand the properties of each defined device. These connections andproperties are specific to the type of device defined. Instances of eachtype of defined device are created and connections between instances aredefined to form an integrated circuit that is to be simulated. Oncecreated, the netlist is read by a simulation program which simulates thedescribed integrated circuit.

In block 220, a first timing analysis is performed on the originalnetlist. In block 222, nominal values for the characteristics of eachdevice as asserted during the design phase of the circuit are providedto the first timing analysis. These assertions are made to set theneeded signal arrival times at the outputs of the defined circuit. Thedevice characteristics may include, but are not limited to,threshold-voltage. In block 224, the first timing analysis is performedusing the asserted nominal characteristics of each device. In block 226,the first timing analysis determines nominal circuit path delays at thetime of production.

The first timing analysis may be static or statistical. A static timinganalysis operates on asserted device characteristics presented as singlefixed-point values and provides nominal circuit path delays presented assingle fixed-point values.

A statistical timing analysis operates on asserted devicecharacteristics presented as a distribution of nominal values for eachdevice, these values representing, as an example but not limited to,samples across a plurality of manufactured circuits or a plurality ofoperating conditions. The statistical timing analysis provides nominalcircuit path delays presented as a distribution of values for eachdevice.

In block 230, a simulation of the original netlist is performed. Inblock 232, a specific or random pattern representing a workload to beseen by the integrated circuit is generated. A person of ordinary skillin the art will note that there are several known methods for generatinga specific pattern that represent a workload to be seen by a circuitunder a defined operating environment. In block 234, the simulation isperformed on the original netlist using the generated pattern. Thissimulation can be a switch based simulation that provides formeasurement of voltages and logic values at the nodes of each deviceduring the simulation. As such, this simulation does not need to havethe added overhead of a timing analysis which is required to determineactual circuit path delays.

In block 240, the voltages and logical values at the nodes of eachdevice are monitored at every time instant throughout the timespan ofthe simulation. These monitored voltage and logic values are used toderive such information as on and off duration times and transition slewof the monitored device. This information then used in conjunction witha degradation model to estimate a change in that device'sthreshold-voltage over one or more lifetimes.

In block 250, the degradation of a characteristic in a device isestimated based on the monitored voltages and logical values. Asdescribed above, a model may represent degradation as a change in adevice's threshold voltage (ΔVT) as a function of operating voltage(V_(dd)), operating temperature (T), on and off duration times (t_(on)and t_(off)) and transition slew (s) over a plurality of lifetimes. Assuch, the voltages and logic values monitored during the simulation areused in conjunction with a degradation model to calculate changes in adevice characteristic representative of degradation at a specificlifetime. Furthermore, a device's degradation calculated at a specificlifetime may then be used to calculate a device's degradation at otherlifetimes.

The calculated change in a device characteristic can be representedeither as a static single-point value or as a distribution of valuesdepending on the type of timing analysis that is to be performed. For astatic timing analysis, the degradation is mapped as a fixedsingle-point offset from a nominal value for one or more of devicecharacteristics. As an example, the calculated offset in thethreshold-voltage of a device is presented as a fixed single-point value(ΔV_(th)) for each device. For a statistical timing analysis, thedegradation is mapped as a distribution specified, for example, by amean, a standard deviation and a distribution type for each device. Asan example, the calculated offset in the threshold-voltage of a deviceis presented as a distribution of values (δV_(th)) for that device.

In block 260, an end-of-life netlist is created reflecting the estimateddegradation of each device within the netlist over a specific lifetime.In other words, in the end-of-life netlist, the characteristics of eachdevice are modified from their nominal values to reflect an estimatedchange in a characteristic as a result of degradation over a specificlifetime. A separate end-of-life netlist is generated for each lifetime.

In block 280, a second timing analysis is performed. In block 282, thesecond timing analysis is performed on each end-of-life netlist. Inblock 284, the second timing analysis determines circuit path delays foreach lifetime defined by a corresponding end-of-life netlist. Thesecircuit path delays correspond to the modified characteristics of eachdevice reflecting the estimated degradation over a specified lifetime.The second timing analysis is usually done in a similar manner as thefirst timing analysis and, as such, may be static or statistical.However, unlike the first timing analysis, the second timing analysis isrun one or more time, depending on the number of end-of-life netlistcreated covering one more specified circuit lifetimes.

As with the first timing analysis, a static second timing analysisoperates on device characteristics presented as fixed single-pointvalues and provides expected circuit path delays presented as fixedsingle-point values for each device. A statistical second timinganalysis operates on device characteristics presented as a distributionof values and provides circuit path delays presented as a distributionof values for each device.

In block 290, the previously determined nominal circuit path delays arecompared to the determined circuit path delays at a specified lifetime.

In another embodiment in accordance with the present principles, ratherthan generate an end-of-life netlist for each specified lifetime, achange in the delay timing of each device is estimated directly from anestimated degradation of a corresponding device.

Referring again to FIG. 2, in block 270, a change in the timing delay ofeach device is derived directly from the estimated degradation in acharacteristic of each device. A timing delay for each device may bederived for each of device lifetime. This estimation may be derivedusing either multiple simulations, analytical equations or both.

In the case of simulations, the device under consideration may besimulated using a transistor level simulator, such as SPICE, under thedevice's specific input slew, load and operating conditions, todetermine a change in timing delay due to the estimated degradation.

In the case of analytical equations, a change in the timing delay of adevice is estimated by mapping the nominal timing delay of the device tothe estimated degradation of that device. Specifically, an analyticalequation defines a non-linear mapping of device timing delay to anestimated change in a device characteristic, such as threshold-voltage.The product of this mapping is a substantially accurate representationof the timing delay of a device resulting from an estimated degradationof the device. The mapping may be of fixed static values or of adistribution of values. As one of ordinary skill in the art will note,there exists a variety of relationships which may define this mapping.

In the case of fixed static values, a fixed static value representingthe nominal delay of a device is mapped to a fixed single-point valuerepresenting the change in a characteristic of that device. The productof this non-linear mapping is a fixed static value representing theexpected timing delay of the device after an estimated degradation hasoccurred.

In the case of a distribution of values, a distribution of valuesrepresenting the nominal delay of a device is mapped to a distributionof values representing changes in a characteristic of the device. Theproduct of this non-linear mapping is a distribution of valuesrepresenting the expected timing delay of the device after degradationof that device has occurred during a defined lifetime.

In block 280, a second timing analysis is performed for each specifiedlifetime. In block 282, the original netlist is simulated and the delayof each circuit path is determined using the modified timing delay forthose devices that have experienced degradation. Any part of theoriginal netlist which has not experienced degradation does need not besimulated again. This second simulation is performed for each specifiedlifetime. In block 284, the second timing analysis determines circuitpath delays over one or more specified lifetimes based on the modifiedtiming delay of each device. As discussed above, the second timinganalysis may be static or statistical.

Referring now to FIG. 3, a block/flow diagram illustrates asystem/method demonstrating an end-of-life statistical timing analysisaccording to an embodiment of the present principles. In block 310,voltages and logic values at the nodes of each device are monitored atevery time instant throughout the timespan of a simulation of a circuitdefinition. The simulation uses a specific pattern representative of aworkload to be seen by the integrated circuit defined by the circuitdefinition. In block 320, a change in the threshold-voltage of eachdevice within the circuit definition is estimated based on the voltagesand logic values monitored during the simulation. The estimated changein threshold-voltage is presented as a distribution of values. In block330, a distribution of the device's nominal timing delays is mapped tothe estimated distribution of values of changes to the threshold-voltageof that device. The product of this non-linear mapping is a distributionof values of timing delays of that device as a result of the estimateddegradation in that device. In block 340, a distribution of values ofthe output transition time of the device is computed as a function of aninput arrival time and the modified timing delays. In block 350, anexpected failure probability of the integrated circuit is presentedbased on a distribution of circuit output times in combination with anexpected lifetime and the expected operational frequency of theintegrated circuit.

As an illustrative example of one possible implementation of theabove-described embodiments, one possible model for degradation due tothe effects of BTI only is

${\Delta \; {V_{T}(t)}} = {{A\; V_{dd}^{a}T^{b}{t_{s}^{n}/1}} + {m\left( \frac{t_{r}}{t_{s}} \right)}^{n}}$

which provides a change in threshold-voltage (ΔV_(T)) as a function ofoperating voltage (V_(dd)), operating temperature (T), stress time(t_(s)) and relax time (t_(r)). The constants A, a, b, n and m aretechnology dependent and fitted using hardware measurements. This modelrepresents degradation as a change in threshold voltage. However, aperson of ordinary skill in the art will note that other models based onother device characteristics may be used to estimate degradation.

In this example, the original netlist is simulated for a period of 2hours at an operating voltage of 1V and the device under question isoperated at a frequency of 2 GHz and experiences an average temperatureof 75 C. It is determined from the voltages and logic levels monitoredat the nodes of the device in question that during the 2 hours period ofthe simulation this device experienced 30 minutes of stress time and 90minutes of relax time. The determined 30 minutes of stress time and 90minutes of relax time are then plugged into the degradation model andthe change in threshold-voltage of the device in question for a lifetimeof 2 hours is calculated. A change in threshold-voltage for each devicewithin original netlist may be similarly calculated.

An end-of-life netlist corresponding to a lifetime of 2 hours is createdin which the nominal threshold-voltage of each device that hasexperienced degradation is modified according to its calculated changein threshold-voltage (ΔV_(T)).

A second timing analysis is then performed on the end-of-life netlist todetermine circuit path delays over the 2 hour lifetime with an operatingvoltage of 1V and an operating frequency of 2 HGz.

Alternatively, a change in the nominal delay time of each device may bederived directly from the calculated change in threshold-voltage forthat device. The change is delay timing may be directly derived by usingan analytical equation to map the device's nominal timing delay to thedevice's calculated change in threshold-voltage. The derived change intiming delay for each device that has experienced degradation is appliedto the original netlist. As second timing analysis is then performed onthose paths within the original netlist which have experienceddegradation to determine circuit path delays at the 2 hour lifetime atan operating voltage of 1V and an operating frequency of 2 HGz.

As another illustrative example of one possible implementation of theabove-described embodiments, it is now desired to determine anend-of-life assessment of the defined circuit slated to run at anoperating voltage of 1.2V and an operating frequency of 3.3 GHz for alifetime of 4 years.

In one implementation, the stress time (t_(s)), relax time (t_(r)) andoperating temperature (T) of the device in question may be directlycalculated from the following relationships,

t _(s)=(t _(s) _(—) _(org) /t _(sim) _(—) _(org))*New_Lifetime*(1+k0*(f_(org) /f _(new))),

t _(r)=(t _(r) _(—) _(org) /t _(sim) _(—) _(org))*New_Lifetime*(1+k0*(f_(org) /f _(new))),

T=T _(org)*(k2*V _(dd) _(—) new^(a) +k3*exp(V _(dd))),

where t_(s) _(—) _(org) is the original stress time, t_(r) _(—) _(org)is the original relax time, t_(sim) _(—) _(org) is the originalsimulation timespan, f_(org) is the original operating frequency,f_(new), is the new operating frequency, T_(org) is the originaloperating temperature and V_(dd) _(—) new is the new operating voltage.Also, where a, k0, k2 and k3 are predetermined coefficients.

Therefore, the change in threshold-voltage (ΔV_(T)) for the device inquestion is slated to run at an operating voltage of 1.2V and anoperating frequency of 3.3 GHz for a lifetime of 4 years is calculatedusing our model based on the following variable,

t _(s)=(30 min/120 min)*4 years*(1+k0*(2 GHz/3.3 GHz),

t _(r)=(90 min/120 min)4 years*(1+k0*(2 GHz/3.3 GHz),

T=75 C*(k2*1.2^(a) +k3*exp(1.2)).

Once the change in threshold-voltage has been calculated, it may be usedto generate another end-of-life netlist at the new lifetime and underthe new operating conditions. As discussed above, the second timing isperformed on the new end-of-life netlist to determine the circuit pathdelays at the new lifetime.

Alternatively, the change in the timing delay of each device that hasexperienced degradation is derived directly from the newly calculatedchange in threshold-voltage for the corresponding device. The secondtiming analysis is then performed on the original netlist using thenewly derived changes in device timing delay.

Moreover, while in this illustrative example the second timing analysiswas described as static, in the embodiments of the present principlesthe second timing analysis may be statistical.

Referring to FIG. 4, a block/flow diagram illustrates a system/methodfor estimating delay deterioration for one or more lifetimes inintegrated circuits due to device degradation according to theembodiments of the present principles. In block 401 and original netlistthat defines an integrated circuit is provided. In block 410, a patterngenerator generates a specific pattern based on a workload to be seen bythe integrated circuit. In block 420, a simulator simulates the originalnetlist. In block 430, a first timing analyzer generates a nominaltiming delay for each device defined within the original netlist. Thenominal timing delay of each device may be presented either as fixedstatic value or as a distribution of values. In block 440, a monitormonitors the voltages and logic values at the nodes of each device atevery time instant during the timespan of the simulation. In block 450,a degradation estimator estimates the degradation of each device basedon the voltages and logic values monitored during the simulation. Theestimated degradation of each device may be presented either as a fixedstatic value for each device or as a distribution of values for eachdevice. In block 460, a netlist generator generates an end-of-lifenetlist in which one or more characteristics of each device have beenmodified to reflect the estimated degradation of each device. The one ormore modified device characteristics may be presented as either a fixedstatic value for each device or as a distribution of values for eachdevice. In block 470, a timing delay estimator estimates a timing delayfor each device directly from the estimated degradation of acorresponding device. The resulting timing delay for each device may bepresented as either a fixed static value for each device or as adistribution of values for each device. The timing delay of each deviceis derived using either equation based fitting or multiple simulationcalls or both. In block 480, a second timing analyzer determines circuitpath delays based either on the end-of-life netlist generated by thenetlist generator or the modified timing delays of each device. Theresulting circuit path delays determined by the second timing analyzermay be presented either as a fixed static value for each circuit path oras a distribution of values for each circuit path.

A system for processing the methods of estimating delay deterioration inintegrated circuits due to device degradation according to theembodiments of the present invention may be implemented using a varietyof appropriate computing system.

FIG. 5 illustrates a computer system for implementing the methods ofestimating delay deterioration for one or more lifetimes in integratedcircuits due to device degradation according to the embodiments of thepresent principles.

Referring now to FIG. 5, a schematic of an illustrative computing systemis shown in accordance with the present principles. Computing system 500is only one example of a suitable computing system and is not intendedto suggest any limitation as to the scope of use or functionality ofembodiments of the invention described herein. Regardless, computingsystem 500 is capable of being implemented and/or performing any of thefunctionality set forth hereinabove.

In computing system 500 there is a computer system/server 512, which isoperational with numerous other general purpose or special purposecomputing system environments or configurations. Examples of well-knowncomputing systems, environments, and/or configurations that may besuitable for use with computer system/server 512 include, but are notlimited to, personal computer systems, server computer systems, thinclients, thick clients, hand-held or laptop devices,microprocessor-based systems, set top boxes, programmable consumerelectronics, network PCs, minicomputer systems, mainframe computersystems, and distributed cloud computing environments that include anyof the above systems or devices, and the like.

Computer system/server 512 may be described in the general context ofcomputer system-executable instructions, such as program modules, beingexecuted by a computer system. Generally, program modules may includeroutines, programs, objects, components, logic, data structures, and soon that perform particular tasks or implement particular abstract datatypes. Computer system/server 512 may be practiced in distributednetwork computing environments where tasks are performed by remoteprocessing devices that are linked through a communications network.

As shown in FIG. 5, computer system/server 512 in computing system 500is shown in the form of a general-purpose computing device. Thecomponents of computer system/server 512 may include, but are notlimited to, one or more processors or processing units 616, a systemmemory 528, and a bus 518 that couples various system componentsincluding system memory 528 and processing units 516.

Bus 518 represents one or more of any of several types of busstructures, including a memory bus or memory controller, a peripheralbus, an accelerated graphics port, and a processor or local bus usingany of a variety of bus architectures. By way of example, and notlimitation, such architectures include Industry Standard Architecture(ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA)bus, Video Electronics Standards Association (VESA) local bus, andPeripheral Component Interconnects (PCI) bus.

Computer system/server 512 typically includes a variety of computersystem readable media. Such media may be any available media that isaccessible by computer system/server 512, and it includes both volatileand non-volatile media, removable and non-removable media.

System memory 528 can include computer system readable media in the formof volatile memory, such as random access memory (RAM) 530 and/or cachememory 532. Computer system/server 512 may further include otherremovable/non-removable, volatile/non-volatile computer system storagemedia. By way of example only, storage system 534 can be provided forreading from and writing to a non-removable, non-volatile magnetic media(not shown and typically called a “hard drive”). Although not shown, amagnetic disk drive for reading from and writing to a removable,non-volatile magnetic disk (e.g., a “floppy disk”), and an optical diskdrive for reading from or writing to a removable, non-volatile opticaldisk such as a CD-ROM, DVD-ROM or other optical media can be provided.In such instances, each drive can be connected to bus 518 by one or moredata media interfaces. As will be further depicted and described below,memory 528 may include at least one program product having a set (e.g.,at least one) of program modules that are configured to carry out thefunctions of embodiments of the invention.

Program/utility 540, having a set (at least one) of program modules 542,may be stored in memory 858, such program modules 542 are by way ofexample, but not limited to, an operating system, one or moreapplication programs, other program modules, and program data. Each ofthe operating system, one or more application programs, other programmodules, and program data or some combination thereof, may include animplementation of a networking environment. Program modules 542generally carry out the functions and/or methodologies of embodiments ofthe invention as described herein. These functions may include adegradation estimator 543, a timing delay estimator 544, a netlistgenerator 545 and a timing analyzer 546.

Computer system/server 512 may also communicate with one or moreexternal devices 514 such as a keyboard, a pointing device, a display524, etc.; one or more devices that enable a user to interact withcomputer system/server 512; and/or any devices (e.g., network card,modem, etc.) that enable computer system/server 512 to communicate withone or more other computing devices. Such communication can occur viaInput/Output (I/O) interfaces 522. Still yet, computer system/server 512can communicate with one or more networks such as a local area network(LAN), a wide area network (WAN), and/or a public network (e.g., theInternet) via network adapter 520. As depicted, network adapter 520communicates with the other components of computer system/server 512 viabus 518. It should be understood that although not shown, other hardwareand/or software modules could be used in conjunction with computersystem/server 512. Examples, include, but are not limited to: microcode,device drivers, redundant processing units, external disk drive arrays,RAID systems, tape drives, and data archival storage systems, etc.

Having described preferred embodiments of a methodology and system forestimating delay degradation in integrated circuits due to devicedegradation (which are intended to be illustrative and not limiting), itis noted that modifications and variations can be made by personsskilled in the art in light of the above teachings. It is therefore tobe understood that changes may be made in the particular embodimentsdisclosed which are within the scope of the invention as outlined by theappended claims. Having thus described aspects of the invention, withthe details and particularity required by the patent laws, what isclaimed and desired protected by Letters Patent is set forth in theappended claims.

What is claimed is:
 1. A system for estimating delay deterioration in anintegrated circuit comprising: a degradation estimator for estimatingdegradation for each of one or more lifetimes in at least onecharacteristic of each device defined within the integrated circuitusing voltages and logic values monitored during a simulation of theintegrated circuit; a netlist generator for generating an end-of-lifenetlist for each of the one or more lifetimes in which the at least onedevice characteristic of each device has been modified to reflect eachof the estimated degradations; and a timing analyzer for performing atiming analysis on each of the end-of-life netlists to determine staticor statistical circuit path delays over the one or more lifetimes. 2.The system of claim 1, wherein the at least one characteristic includesthreshold-voltage as a function of at least one of a device's operatingvoltage, operating temperature, on and off duration times and transitionslew.
 3. The system of claim 1, further including a probabilityestimator for estimating the probability of failure of the integratedcircuit over each of the one or more lifetimes for a given operatingspecification based on each of the determined circuit path delays. 4.The system of claim 1, wherein the simulation uses a specific patternrepresentative of a workload to be seen by the integrated circuit. 5.The system of claim 1, wherein the netlist generator generates theend-of-life netlists based on an original netlist file that describesthe devices included in the integrated circuit.
 6. The system of claim5, wherein the devices in the integrated circuit include both analog anddigital devices.
 7. The system of claim 5, wherein the netlist comprisesa listing of possible connections between devices and properties of eachdevice.
 8. The system of claim 7, wherein the timing analyzer furtherperforms a first timing analysis on the original netlist file.
 9. Thesystem of claim 8, wherein the first timing analysis uses the propertiesof each device to determine nominal circuit path delays at productiontime.
 10. The system of claim 8, wherein the timing analyzer performstiming analyses using static timing analysis that operates on asserteddevice characteristics presented as single, fixed-point values andprovides nominal circuit path delays as single, fixed-point values. 11.The system of claim 8, wherein timing analyzer performs timing analysesusing statistical timing analysis that operates on asserted devicecharacteristics presented as a distribution of nominal values for eachdevice and provides nominal circuit path delays as a distribution ofvalues for each device.
 12. A system for estimating delay deteriorationin an integrated circuit comprising: a degradation estimator forestimating future degradation for each of one or more lifetimes in atleast one characteristic of each device defined within the integratedcircuit using voltages and logic values monitored during a simulation ofthe integrated circuit; a netlist generator for generating anend-of-life netlist for each of the one or more lifetimes, based on anoriginal netlist file that describes the devices included in theintegrated circuit, in which the at least one device characteristic ofeach device has been modified to reflect each of the estimateddegradations; and a timing analyzer for performing a first timinganalysis on the original netlist file and one or more second timinganalyses on each of the end-of-life netlists to determine static orstatistical circuit path delays over the one or more lifetimes.
 13. Thesystem of claim 12, wherein the at least one characteristic includesthreshold-voltage as a function of at least one of a device's operatingvoltage, operating temperature, on and off duration times and transitionslew.
 14. The system of claim 12, further including a probabilityestimator for estimating the probability of failure of the integratedcircuit over each of the one or more lifetimes for a given operatingspecification based on each of the determined circuit path delays. 15.The system of claim 12, wherein the simulation uses a specific patternrepresentative of a workload to be seen by the integrated circuit. 16.The system of claim 12, wherein the devices in the integrated circuitinclude both analog and digital devices.
 17. The system of claim 12,wherein the netlist comprises a listing of possible connections betweendevices and properties of each device.
 18. The system of claim 12,wherein the first timing analysis uses the properties of each device todetermine nominal circuit path delays at production time.
 19. The systemof claim 12, wherein the timing analyzer performs timing analyses usingstatic timing analysis that operates on asserted device characteristicspresented as single, fixed-point values and provides nominal circuitpath delays as single, fixed-point values.
 20. The system of claim 12,wherein timing analyzer performs timing analyses using statisticaltiming analysis that operates on asserted device characteristicspresented as a distribution of nominal values for each device andprovides nominal circuit path delays as a distribution of values foreach device.